Help: What's the difference between functional simulation and timing one

Functional Simulation simply tests the logic "functional" operation of the circuit. There is no consideration for delay through the internal logic or the routing dealy paths associated with where the placer and the router interconnect things.

It simply allows you to see that what you think you are coding provides the results you are intending.

With Timing Simulation, the delay asociated with the logic elements and the interconnect routing are taken into consideration (based on the speed grade of the chip selected).

Delays may result in signals not meeting setup time, etc. which could explain wehy your results do not look as expected.

In order to 'help' the Place and Route phase of the Quartus tools achieve the results you desire, you will need to place timing assignments on your design. This is not doen wwith the TimeQuest timing analysis tool. You specifiy the desired clock frequency, and the Desired inout and output delays on and off chip as a minimum. There is a good Free Online training on the subject on the Altera WEB site under training.

TimeQuest can save an .sdc file, which you add to your design as a design input file, and then you place and route the design and inspect reports to see if you have met all 'requested' timing.

Then you can runt hte Timing Simulation and all should be good.

Enjoy.