Help needed

Hi all,

I am trying to implement a 32 bit RISC processor on a Cyclone II FPGA. I'm using quartus 13.0 sp1 tool. I have coded a single stage of the pipeline so far. I have pasted the code below. The errors I have been getting are at lines 5&6

Error (12002): Port "IF_out" does not exist in macrofunction "d1"

Error (12002): Port "RR_in" does not exist in macrofunction "d1"

Error (12002): Port "IF_out" does not exist in macrofunction "i1"

Error (12002): Port "pc_fetch" does not exist in macrofunction "i1"

module risc32(pc_fetch,clk);

input clk;

input [31:0] pc_fetch;

reg[31:0] IF_out;

IF_decode i1 (.pc_fetch(in),.IF_out(out));

d_flip_flop d1 (.IF_out(d),.RR_in(q),.clk(clk));

endmodule

module d_flip_flop(d,q,clk);

input d,clk;

output reg q;

always@(posedge clk)

q<=d;

endmodule

module IF_decode(in,out);

input[31:0] in;

output reg[31:0] out;

reg [4:0] opcode;

wire [3:0]op_ext;

wire[22:0]arg;

wire [1:0]width;

wire [3:0] rd_reg0_num, rd_reg1l_num, rd_reg2_num;

wire [9:0]ofs;

wire [2:0]shift;

wire[7:0]k;

wire[4:0]k_shift;

always@(in, opcode)

begin

case(in[4:0])

5'b11101: out[4:0] = opcode;

5'b11110: out[4:0]= opcode;

5'b00000: out[4:0]=opcode;

5'b0xx01: out[4:0]=opcode;

5'b01110: out[4:0]=opcode;

default: out[31:0] = 32'bz;

endcase

end

endmodule