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Altera_Forum's avatar
Altera_Forum
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10 years ago

Help needed

Hi all, I am trying to implement a 32 bit RISC processor on a Cyclone II FPGA. I'm using quartus 13.0 sp1 tool. I have coded a single stage of the pipeline so far. I have pasted the code below....
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

the . name refers to the port name on the module, not the local varaible. Plus RR_in isnt declared in any of your code.