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Altera_Forum
Honored Contributor
Honored ContributorHelp needed
Hi all, I am trying to implement a 32 bit RISC processor on a Cyclone II FPGA. I'm using quartus 13.0 sp1 tool. I have coded a single stage of the pipeline so far. I have pasted the code below....
Altera_ForumHonored Contributor
Honored Contributorthe . name refers to the port name on the module, not the local varaible. Plus RR_in isnt declared in any of your code.
