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Altera_Forum
Honored Contributor
17 years agoCan I use the same strategy if I have parallel data to be passed from one clock domain to the other?
thx --- Quote Start --- Hi, You need to register the toggle signal through a cascade of two registers clocked by the 80MHz then use it in the FSM. Other alternatives include having 80MHz only and generating clock enable at 2.66MHz(using modulo adder that increments by 266 and overflows at 8000 then use the oveflow pulse as clock enable). example of two stage cascade: process(reset, clk_80) if(reset = '1')then toggle_1d <= '0'; toggle_2d <= '0' elsif(rising_edge(clk_80))then toggle_1d <= toggle; toggle_2d <= toggle_1d; end if; end process; then use toggle_2d as your FSM signal. You may still get warnings but you may ignore them. Kaz --- Quote End ---