help needed: passing toggle signals cross clock domain

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Hi all...I have a process running at clock A (2.667MHz) which will generate a toggle signal X and I need this signal to pass to clock domain B (80MHz) which a FSM is updating its state according to this X...Time Quest is always giving me critical warnings saying that I have setup time voilation. I checked it out, it's all cross clock domain signals..

so question: how do I effectively pass my toggle switch signal? I found something in "The Ten Commandments of Excellent Design-VHDL Code Examples"..but don't quite understand how to do it...any suggestion/advice?

Thanks

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Hi,

the problem is that your two clocks are total asynchronously. That means that the phase between the clock edge is not fixed. Therefore the reported timing violations, but you can cut the pathes in the timing analysis. You have to design a clock domain crossing here. You are sending a single bit signal from a lower clock domain to a faster clock domain. So it should be sufficient to latch-in the signal with two FF running with the higher clock. I believe you can find a lot of stuff in this forum regarding clock domain crossing.