Altera_ForumHonored Contributor9 years agoHelp needed in VHDL Testbench Hi all, I have written the testbench file in such a manner that I need to perform updowncounting and downcounting based on the value of dir_s. But the problem is, when I execute the code, the di...Show More
Altera_ForumHonored Contributor9 years agoYou said you dont have the source code for tdc_readout, how are you simulating it?
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