Help - Quartus never completes Analysis/Synthesis

For anyone interested - here's the entire module. It's instantiated only ONE place in the 'main' module. There are 2 lines of code highlighted. If either one is changed from what it is to what I want, the compile hangs 2 minutes in, on "Duplicate registers merged into single register". When it doesn't hang, it generates the "duplicate registers" message 2 more times, and then begins inferring, elaborating, and instantiating megafunctions.

help? 8-}

/j

library ieee;

use IEEE.std_logic_signed.all;

use ieee.std_logic_1164.all;

-- saturates top sat_wid bits and then delivers next data_out_len significant bits

entity shft_rnd_sat0 is

generic (

data_in_len : integer;

data_out_len : integer;

rshift : integer

);

port (

data_in : in std_logic_vector (data_in_len -1 downto 0);

data_out : out std_logic_vector (data_out_len -1 downto 0)

);

end shft_rnd_sat0;

architecture rtl of shft_rnd_sat0 is

constant din_shift_len : integer := data_in_len - rshift;

-- constant sat_wid : integer := din_shift_len - data_out_len; -- GOOD

constant sat_wid : integer := din_shift_len - data_out_len-1; -- WRONG, but permits compile

signal data_in_shift_rnd : std_logic_vector (din_shift_len-1 downto 0);

signal data_in_shift : std_logic_vector (din_shift_len-1 downto 0);

signal sat_val : std_logic_vector (sat_wid downto 0);

begin

-- round operation

data_in_shift_rnd <= (data_in (data_in_len -1 downto rshift)) + ((data_in_len-rshift-1 downto 1 => '0') & '0'); -- WRONG, but permits compile

-- data_in_shift_rnd <= (data_in (data_in_len -1 downto rshift)) + ((data_in_len-rshift-1 downto 1 => '0') & '1'); -- GOOD

process (all)

begin

-- if the rounding bit is 0, or if the value is

-- max and can't be rounded, just shift into smaller container

if ((data_in(rshift-1) = '0') or

(data_in (data_in_len -1 downto rshift) = ('0' & (data_in_len-rshift-2 downto 0 => '1')))) then

data_in_shift <= data_in (data_in_len -1 downto rshift);

else

-- otherwise shift and round into smaller container

data_in_shift <= data_in_shift_rnd(din_shift_len-1 downto 0);

end if;

-- saturate smaller container downto output width

sat_val <= data_in_shift (din_shift_len-1 downto din_shift_len - sat_wid-1);

if (((sat_val = (sat_val'length-1 downto 0 => '0')) or

(sat_val = (sat_val'length-1 downto 0 => '1'))) or (sat_wid = 0)) then

data_out <= data_in_shift (data_out_len - 1 downto 0);

elsif (sat_val(sat_val'length-1) = '1') then

data_out <= ('1' & (data_out_len-2 downto 1 => '0') & '1'); -- symetric

else

data_out <= ('0' & (data_out_len-2 downto 0 => '1'));

end if;

end process;

end;