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AHoll13's avatar
AHoll13
Icon for New Contributor rankNew Contributor
6 years ago

Hello. I'm new to FPGAs/CPLDs, and am doing a project with the MAX V 5M160ZE64A5N CPLD and am getting timing failures with a 100MHz clock.

The 100MHz clock is clocking I/O and generating time delays in the logic circuit. I have used the Timing Analyzer and SDC file to constrain the clock, as well as the I/O, however I am getting errors ...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

Do you have any updates?

Thanks.

Best regards,

KhaiY

  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi,

    We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you

    Best regards,

    KhaiY