Forum Discussion
AHoll13
New Contributor
New ContributorHello. I'm new to FPGAs/CPLDs, and am doing a project with the MAX V 5M160ZE64A5N CPLD and am getting timing failures with a 100MHz clock.
The 100MHz clock is clocking I/O and generating time delays in the logic circuit. I have used the Timing Analyzer and SDC file to constrain the clock, as well as the I/O, however I am getting errors ...
sstrell
Super Contributor
Super ContributorNo, clrn is for resetting a register. It is typically only used at reset time and used with a separate reset signal that goes low at reset time and then is held high during normal operation. D flip flops are cleared during normal operation by the D input being low at a clock toggling edge (positive or negative edge depending on the flip flop).
And as I stated, the fan-out of the data/clrn signal may be an issue now, not the clock signal, so I'm not sure I understand your second paragraph.
Can you also clarify exactly which paths are failing timing? It's difficult to correlate your timing report with the tiny text on the schematic.
#iwork4intel
