Forum Discussion
AHoll13
New Contributor
New ContributorHello. I'm new to FPGAs/CPLDs, and am doing a project with the MAX V 5M160ZE64A5N CPLD and am getting timing failures with a 100MHz clock.
The 100MHz clock is clocking I/O and generating time delays in the logic circuit. I have used the Timing Analyzer and SDC file to constrain the clock, as well as the I/O, however I am getting errors ...
AHoll13New Contributor
New ContributorAn update - I have optimised my logic circuit design. I still get timing path failures when using a 100MHz clock, yet a 50MHz clock has zero failed timing paths. However, I now have zero clock skew. See attached my new failing paths in Timing Analyser and new logic circuit (which is again repeated 6 times, with a shared clock).
Any help rectifying my timing path failures for a 100MHz clock would be greatly appreciated.
Many thanks
