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AHoll13's avatar
AHoll13
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5 years ago

Hello. I'm new to FPGAs/CPLDs, and am doing a project with the MAX V 5M160ZE64A5N CPLD and am getting timing failures with a 100MHz clock.

The 100MHz clock is clocking I/O and generating time delays in the logic circuit. I have used the Timing Analyzer and SDC file to constrain the clock, as well as the I/O, however I am getting errors ...
sstrell's avatar
sstrell
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5 years ago

Just from that timing report, you have a huge amount of clock skew, almost 5 ns, between the sources and destinations of the failing paths. How is your clocking set up? Have you gated your clocks for some reason?

#iwork4intel

AHoll13's avatar
AHoll13
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5 years ago

Thanks for the reply. No I haven't gated my clocks, but the clock is fanned out to a total of 96 d-type flip flops.

See attached for my logic diagram. This circuit is duplicated 6 times, all instances of which are identical, but share the same clock.