Forum Discussion
You're now assigning single bit values (HEX0-HEX3) to a 7-bit signal (sseg), so again, your final case statement is only going to work for sseg equal to 0 or 1. Is your case statement supposed to be checking an_temp instead of sseg? That would make more sense. If so sseg is not even needed. Or are you saying that HEX0-HEX3 are supposed to be 4 bit inputs each, like HEX0[3:0] for the first one? It's really not clear what you're trying to do here.
And the errors you've posted don't look like they correspond to this file. They reference some other file named "yet.v" that you haven't posted. The giveaway: "wire" in the first error which isn't even in the code you've posted. Double-click errors to open the correct file and the text editor will highlight where the error is.
#iwork4intel