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Altera_Forum
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13 years ago

HDL with Quartus 10.0 (state machines and counters)

Hi Forum, I am not sure if this the right forum. I am working in a project in which part of the code was written in HDL. There is a state machine, SM, which changes states according to some cou...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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I have used one of the states of the SM to clock the counter (counter[].clk= (State_machine==STATE3)).

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That's definitely not a good way to design a FSM. All FFs holding the state variable and additional information should be clocked by a single system clock.