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Altera_Forum
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13 years ago

HDL with Quartus 10.0 (state machines and counters)

Hi Forum, I am not sure if this the right forum. I am working in a project in which part of the code was written in HDL. There is a state machine, SM, which changes states according to some cou...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

That sounds like AHDL, which is a depricated language. You cannot simulate it so debugging is harder. It also has some quirks you need to be aware of. You would be better off using either VHDL or verilog, as you can simulate them in modelsim, which makes debugging a whole lot easier.,

Could you post the code and specific problems as we may be able to help.