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(Well, there's Native Link but ignore it for the moment.)
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.... and not ignoring NativeLink, here the high level flow of what you do:
1) write your FPGA top-level as you normally would for synthesis.
2) either write your testbench from scratch, or after it successfully compiles you can use within Quartus menu Processing->Start->Start Test Bench Template Writer. All this is going to do for you is inspect your toplevel and generate a blank VHDL testbench file that instantiates your toplevel and provides signals with correct names. It's useful if you're starting from scratch, but it's entirely possible your ISE VHDL test benches just may need minor edits?
3) write the VHDL to apply the behavior you want applied for your testbench
4) configure NativeLink to run your testbench. Assignments->Settings->EDA Tool Settings->Simulation. In the bottom section related to NativeLink, select the "Compile Test Bench" radio button and then click on Test Benches... and New.... and fill out the dialog box with information about your testbench.
5) within Quartus, click Tools->Run Simulation Tool->RTL Simulation. This will launch Modelsim, compile the simulation files, add the top-level signals to the waveform, and run your simulation.
Steps 1-4 are one-time tasks, while (5) you can do for the life of your project. The (small?) benefit that NativeLink adds is that as your FPGA project contents grow, Quartus will update the Modelsim scripts so you can somewhat eliminate duplication of effort in maintaining Quartus and Modelsim projects.
Attached is a trivial Quartus project with a single register and a testbench created using the template writer and then customized to add the CLK, ACLR, D input generation. Open the .qar in Quartus, compile the project, and then launch the RTL Simulation to see it run.
I think if the original poster follows up with a description/example of how XIlinx does things and the shortcomings with the Altera approach, then others can probably suggest relatively simple alternatives.
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