HDL Testbench in ModelSim Altera Edition

I am trying to simulate through modelsim using a testbench that is currently run using Xilinx ISE by setting it as the top level module and running the simulation.

Initially I did the same thing in Quartus II and attempted RTL simulation and generated errors, my understanding is Quartus II does not support simulation in the same fashion as Xilinx ISE and that additional steps in ModelSim Altera Edition are required. If available I was looking for guidance on moving designs from Xilinx to Altera.

For example, if I had a simple counter and instantiated it in a top level testbench file along with the following process the Xinlinx ISE will simulate the counter, my understanding is Quatrus II requires a more steps in the simulation flow and wanted to see if there was decent documentation on changing over.

process(CLK)

begin

clk <= not clk after 20 ns;

end process