Honored Contributor
Honored Contributor# Reading C:/altera/15.0/modelsim_ase/tcl/vsim/pref.tcl# do sum_fix_run_msim_rtl_verilog.do# if {[file exists rtl_work]} {# vdel -lib rtl_work -all# }# vlib rtl_work# vmap work rtl_work# Model Technology ModelSim PE vmap 10.3d Lib Mapping Utility 2014.10 Oct 7 2014# vmap -modelsim_quiet work rtl_work # Copying C:/altera/15.0/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini# Modifying modelsim.ini# ** Warning: Copied C:/altera/15.0/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini.# Updated modelsim.ini.# # vlog -vlog01compat -work work +incdir+C:/altera/15.0/PROYECTOS/Oper_fixed {C:/altera/15.0/PROYECTOS/Oper_fixed/sum_fix.v}# Model Technology ModelSim ALTERA vlog 10.3d Compiler 2014.10 Oct 7 2014# Start time: 12:07:41 on Feb 09,2016# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/altera/15.0/PROYECTOS/Oper_fixed" C:/altera/15.0/PROYECTOS/Oper_fixed/sum_fix.v # -- Compiling module sum_fix# # Top level modules:# sum_fix# End time: 12:07:41 on Feb 09,2016, Elapsed time: 0:00:00# Errors: 0, Warnings: 0# # vlog -vlog01compat -work work +incdir+C:/altera/15.0/PROYECTOS/Oper_fixed/simulation/modelsim {C:/altera/15.0/PROYECTOS/Oper_fixed/simulation/modelsim/sum_fix_tb.vt}# Model Technology ModelSim ALTERA vlog 10.3d Compiler 2014.10 Oct 7 2014# Start time: 12:07:41 on Feb 09,2016# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/altera/15.0/PROYECTOS/Oper_fixed/simulation/modelsim" C:/altera/15.0/PROYECTOS/Oper_fixed/simulation/modelsim/sum_fix_tb.vt # -- Compiling module sum_fix_vlg_tst# # Top level modules:# sum_fix_vlg_tst# End time: 12:07:41 on Feb 09,2016, Elapsed time: 0:00:00# Errors: 0, Warnings: 0# # vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver -L rtl_work -L work -voptargs="+acc" sum_fix_tb.vt# # add wave *# view structure# view signals# .main_pane.objects.interior.cs.body.tree# run -all# ** Error: No Design Loaded!# Error in macro ./sum_fix_run_msim_rtl_verilog.do line 17# No Design Loaded!# while executing# "run -all"
