Forum Discussion
CheepinC_altera
Regular Contributor
6 years agoHi Sam,
As I understand it, you observe different in compilation observation between Q18.1 vs 19.1. Your design is passing compilation in 18.1 but seems to fail in 19.1. To facilitate further debugging, would you mind to share with me a simple test design which could replicate your observation? Please share with me also the specific assignment that you use to set the DSP limit.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin