Hardware Acceleration of instruction set. Help finding literature?

Hi.

I am currently doing literary studies in preparation of writing my master thesis. The thesis is focused on hardware acceleration on instruction level granulation. This basically means that i am going to be running a bunch of benchmarks on a specific CPU core IP. Then identify what instructions are executed often and if any of them benefit from either being implemented in a HW accelerator individually or grouped. I am having a hard time finding scientific papers and/or books related to instruction set level HW acceleration (techniques, approaches, examples?). Can anyone here help in pointing me to existing literature on the subject?

Thanks a lot!