Forum Discussion
Hi Everyone,
I know I'm late to this party, but I just wanted to say that the issue for me was a RESET line not in the correct state. I'm using a custom board so it was a little more difficult to track down. What I did to find the issue was in HDL I forced the reset line to the correct state and everything just worked.
I'm also surprised that a lot of issues on this forum go unanswered. If people came back and just mention their solutions, it would also really help.
This is unrelated, but the more I use Altera, the more I like Xilinx instead. Altera's error message made no sense, the system ID and timestamp mismatach. What does that really mean? Did I screw up the Qsys design? My JTAG debugger is reading the wrong info? I've had this reset issue with Xilinx before, and the error message reads, cannot communicate with target, processor maybe in reset, check power.
Anyway, just my thoughts, have a nice day!