global clock lines

I think you are saying you want to make a "Global Signal" assignment to clk_2. Because clk_2 is a register, most likely "clk_2" is part of a name in the node list (names of combinational signals tend to be harder to recognize in the node list). The first thing I would try is "*clk_2*" (without the quotes) in the Node Finder "Design Entry (all names)" filter. The first wildcard takes care of any hierarchy. The second wildcard takes care of any suffix that might be added to the name during compilation. Sometimes another Node Finder filter is needed to get the correct form of the name, but "Design Entry (all names)" is good enough for me most of the time.

You said "work with en". The following comments are in case you are trying to use my clock enable suggestion instead of using a ripple clock.

If clk_2 is being used as a clock enable rather than as an actual clock, the timing might be better with it nonglobal. If it has a high fan-out, there might be significant interconnect delay from nonglobal routing. However, a global has a significant delay for the global buffer itself. Usually the biggest advantage of global routing is to minimize skew, and skew does not matter for a clock enable as it does for a clock. Once you've figured out how to control the global routing usage, you can try the clock enable both global and nonglobal to see which has better timing.

Your VHDL is creating a clock, not a clock enable, waveform for clk_2. The clock enable for a divide-by-n should be asserted every nth clock cycle of the full-speed clock (http://www.alteraforum.com/forum/showthread.php?p=2153#post2153). Instead of "clk_2<=not(clk_2);", you would assert clk_2 for one period of clk1 using "if (counter=<n_value>)" to do the divide-by-n.

If clk_2 is a clock enable, then registers using the clock enable would have something like the following code that is based on a Quartus VHDL template. The registers using the clock enable most likely should be clocked by clk1, the same clock used by the clk_2 register that drives the clock enable. Even though these registers are clocked by clk1, you can use multicycles to tell Quartus they may in effect run at the clk_2 rate. The post noted just above shows how to do the multicycles in TimeQuest. If you are using the Classic Timing Analyzer with the default multicycle hold, then you can use the "Clock Enable Multicycle" assignment with the clock enable signal name in both the "from" and "to" fields.

process (clk1, reset)
begin
    if (reset = '0') then
        <register_variable> <= '0';
    elsif (rising_edge(clk1)) then
        if (clk_2 = '1') then
            <register_variable> <= <data>;
        end if;
    end if;
end process;