global clock lines

Brad thank you very much... I changed the second ff to work with en (the new clk)

but I can't manage to define internal signal as global clk

signal clk_2 : std_logic;

begin

process(reset,clk1)

begin

if reset='1' then

counter<="0000000000000000000000001";

-- counter<="01";

clk_2<='0';

elsif rising_edge(clk1) then

-- if (conv_integer(counter) mod 2=0) then

if (counter="1011111010111100001000000") then

clk_2<=not(clk_2);

counter<="0000000000000000000000001";

else

counter<=counter+1;

end if;

end if;

(the program changes 50 MHz->2 Hz)

I can't detect this signal in the Assignment editor, only the signals in entity...

tenx

ari