global clock lines

Hi,

Thank you very much for your answer...

What I ment is that I use 50 MHz clk (DE2 board), change the frequency in the first component to 2 Hz by using counters (not PLL) and then use the new clk frequency as

the input clk to the next component (7 segment decoder)

I want to define this connection as global clock becuase it work but I get his message:

Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew

Info: Detected ripple clock "frequency_change:U1|clk_2" as bufferWarning:

tenx,

ari