Global assignment being deleted/changed when using same source in multiple VHDL libraries.

Right thanks for that explanation, perhaps I can explain deeper and maybe it relates to what you are saying. But before I do, would your explanation justify the design compiling fine the first time and not the second?

Anyway here's a more detailed look at the VHDL files themselves.

I have a orderbook entity which accepts input t_messages record.

Two different records with the same t_messages name are defined in two packages with the same name orderbook_pkg - in different files, .e.g pkgA.vhd and pkgB.vhd.

The orderbook entity (file) has use work.orderbook_pkg and uses orderbook_pkg.t_messages. Note no library specification as work should denote the current compiling context/workspace (please correct me if I misunderstand this).

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.orderbook_pkg;
 
entity orderbook is
     port(
        i_messages : in orderbook_pkg.t_messages;
...

LibA is compiled with orderbook file + pkgA.vhd

LibB is compiled with orderbook file + pkgB.vhd

set_global_assignment -name VHDL_FILE pkgA.vhd -library LibA
set_global_assignment -name VHDL_FILE orderbook.vhd -library LibA
set_global_assignment -name VHDL_FILE pkgB.vhd -library LibB
set_global_assignment -name VHDL_FILE orderbook.vhd -library LibB

top is compiled in another MainLib (no work libs in this project)

top creates signals for the messages:

library LibA;
library LibB;
...
signal msgA : LibA.orderbook_pkg.t_messages;
signal msgB : LibB.orderbook_pkg.t_messages;

top also instantiates the two entities using library names:

libAEntity : entity LibA.orderbook(rtl)
    port map(
        i_messages => msgA,
...
...
libBEntity : entity LibB.orderbook(rtl)
    port map(
        i_messages => msgB,
...

It compiles fine the first time from a clean start. A clean start means if you remove all the files in the db directory. However, without cleaning the db directory, on a second rerun when its compiling libBEntity:LibB.orderbook it picks up pkgA.orderbook_pkg.

Info (12129): Elaborating entity "orderbook" using architecture "A:rtl" for hierarchy "orderbook:libBEntity" File: C:/temp/top.vhd Line: 1567
Warning (10542): VHDL Variable Declaration warning at pkgA.vhd(346): used initial value expression for variable "v_dummy" because variable was never assigned a value File: C:/temp/pkgA.vhd Line: 346
...
...
Error (12002): Port "i_messages.orderB.eom" does not exist in macrofunction "libBEntity" File: C:/temp/top.vhd Line: 1567
Error (12002): Port "i_messages.orderB.eop" does not exist in macrofunction "libBEntity" File: C:/temp/top.vhd Line: 1567
...

And eventually falls over because the records/ports are different.

Hopefully I have summarised this, if you can assess the method I am using based on your previous explanation - hopefully you can confirm or deny that it is the same case. Note it passes with a clean db directory - which is the current workaround that I am using. Thank you for you help.