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HHami3's avatar
HHami3
Icon for New Contributor rankNew Contributor
6 years ago

Global assignment being deleted/changed when using same source in multiple VHDL libraries.

Hi there, I have an entity in a file which is compiled into two different VHDL libraries. I also have two different packages with the same name, for each library which are input into the entity. Whe...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

You have to ensure that you use a distinct VHDL Namespace for Each Library. For the Example RTL, the analyzer searches all libraries in an unspecified order until the analyzer finds package utilities_pack and uses items from that package. If another library, for example projectLib also contains utilities_pack, the analyzer may use this library instead of myLib.utilites_pack if found before the analyzer searches myLib.

Therefore, you have to change the name to a unique name.

Thanks.