glitches in FSM output signals

If you need your outputs to be glitchless (for instance when interfacing to an asynchronous external part that is sensitive to glitches), a simple solution is to register the outputs. Take into account that the outputs will then be delayed one cycle. This is very simple, common, and recommended in many cases

If the extra cycle added makes this solution unworkable, there are manual state machine encoding methods that can prevent glitches by having each output depend on only one state encoding bit (and some inputs, if it is a Mealy machine). This state machine encoding will probably not be the most timing or space efficient.

However, as Brad and Rysc mentioned, you probably don't need to worry about glitches at all, unless you are trying to guarantee specific asynchronous timing.