Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

glitches in FSM output signals

Hello..I have a FSM (mealy type). The FSM is coded as three processes. The first process move the state forward on every rising clock edge. The second process only takes care of the state transition ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

There is a related current thread at http://www.alteraforum.com/forum/showthread.php?t=4121. That person was concerned about glitches on state machine outputs before realizing that the glitches don't matter if the outputs are used only synchronously by feeding registers.

If you are using state machine outputs or any other signal for a clock (usually a bad idea) or asynchronously for something like a reset, then you have to take special measures to prevent the normal glitching that Rysc mentioned.