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Altera_Forum
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13 years ago

Glitch free operation post-mux between two asynchronous clock domains

I have two single-bit signals running in separate clock domains (~39MHz and ~270MHz). Each can be assumed to be arriving from registers. I need to mux these two signals depending on a flag and outp...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

The ~39MHz period in time is roughly 25.77 nS, the 270MHz period in time is roughly 3.7 nS. The 270MHz process will sample 6.96 times per 39MHz clock cycle. IF this were a nice even multiple, I agree that converting the 39MHz signal over to the 270MHz clock domain makes sense. Because it is not, the 39MHz signal no longer has a 25.77nS period. It will now have either a 22.22 nS or a 25.92 nS period (depending on the phase relationship between the 270MHz andd 39MHz clocks at the time of sampling.

This variation between 22.22 nS and 25.92 nS periods is jitter. It falls far outside the allowable jitter to meet specifications.