--- Quote Start ---
I have two single-bit signals running in separate clock domains (~39MHz and ~270MHz). Each can be assumed to be arriving from registers. I need to mux these two signals depending on a flag and output the selected signal on the pin of the FPGA (Cyclone IV for anyone interested). Delay to output is not an issue. The hard part is ensuring the output is glitch free (long after the selection is made). I believe that I need an output register post-mux, but the register would need to have the clock switched between the two clock domains to function properly.
Using an internal PLL to change clocks is not an option. We've used up just about all of the resources available. Sampling the ~39MHz at the ~270MHz rate is also out as I have some fairly tight jitter tolerance that would fail.
I did note the Verilog example of the glitch-free clock mux in the Quartus II Handbook. I think it may be overkill for what I need, but I'm more concerned about steady state behavior more than start-up transients.
Do you think a simple clock mux behavior with a good timequest timing script would work out (or am I just out of luck)? Any suggestions would be helpful.
--- Quote End ---
Though not sure why you think glitch will occur at mux output without any clock but I suggest synchronising slow signal onto fast clock through two stages then clock the mux with fast clock.
Honored Contributor
