Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorGetting 'Timing requirements not met' as critical warning
Hi, I have created a design and would like to compile the design in order to create a binary file for the CPLD. However when I try to compile the design, it outputs a warning saying that the timing r...
Saravana1987
New Contributor
New ContributorHi Sir
When I add the .sdc file with all requirements such as create_clock and clock derivativity I got the same issue timing requirements not met. I got pll with 210MHz , 17ns and another 17ns with 5ns phase difference and the input clock is 50 MHz, will you please guide me in this issue.
Thanks
T.S.Saravana Kumar
When I add the .sdc file with all requirements such as create_clock and clock derivativity I got the same issue timing requirements not met. I got pll with 210MHz , 17ns and another 17ns with 5ns phase difference and the input clock is 50 MHz, will you please guide me in this issue.
Thanks
T.S.Saravana Kumar
sstrell
Super Contributor
Super ContributorProbably should create a new topic here in the forum and include your .sdc file and what you're seeing in the timing analyzer. This is a 6 year old thread.
