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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Getting 'Timing requirements not met' as critical warning

Hi, I have created a design and would like to compile the design in order to create a binary file for the CPLD. However when I try to compile the design, it outputs a warning saying that the timing r...
Saravana1987's avatar
Saravana1987
Icon for New Contributor rankNew Contributor
2 years ago
Hi Sir
When I add the .sdc file with all requirements such as create_clock and clock derivativity I got the same issue timing requirements not met. I got pll with 210MHz , 17ns and another 17ns with 5ns phase difference and the input clock is 50 MHz, will you please guide me in this issue.
Thanks
T.S.Saravana Kumar
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
2 years ago

Probably should create a new topic here in the forum and include your .sdc file and what you're seeing in the timing analyzer. This is a 6 year old thread.