Getting 'Timing requirements not met' as critical warning

Critical Warning (332012): Synopsys Design Constraints File file not found: 'monitor.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.

That's your first problem. You should add an SDC file which at the very least contains a "create_clock" for any clock input, and the commands "derive_pll_clocks -create_base_clocks" (if you have any PLLs) and "derive_clock_uncertainty".

The constraints file tells TimeQuest and Quartus what frequency your clock signals run at so it knows how to optimise and can give you an idea of the whether your design will run correctly without timing issues caused by propagation delays, etc.

Without a constraints file, Quartus assumes all clocks in the design run at 1GHz ("Calling derive_clocks -period 1.0") at which point pretty much every design would fail timing.

Setup slack means the amount of time that a clock signal reached a register in your design *before* the data would have got there. If a clock reaches a register before the data, then the value clocked in will be out of sync or some unknown transition value. This is called a setup timing violation and is the bane of all FPGA designers as it makes your design do highly unpredictable things. Timing violations are bad! The fact that your worst case slack is -8ns means your design could probably run at 100MHz, but not at 1GHz - I calculated this as dropping the clock frequency to 100MHz would give you an extra +9ns slack compared with 1GHz which would nicely absorb the negative slack (this is just a simplified example of what it means).

An example file would be:

# 
#  Design Timing Constraints Definitions
# 
set_time_format -unit ns -decimal_places 3
# #############################################################################
#  Create Input reference clocks
create_clock -name {clkin_50} -period 20.000 -waveform { 0.000 10.000 } 
# #############################################################################
#  Now that we have created the custom clocks which will be base clocks,
#  derive_pll_clock is used to calculate all remaining clocks for PLLs
derive_pll_clocks -create_base_clocks
derive_clock_uncertainty

Here I create a clock called "clkin_50" (you can name it whatever you like), specify that it is 50MHz (20ns period), specify it is 50% duty cycle (rising edge at 0ns, falling edge at 10ns), and instruct that the port that the clock is located at (e.g. FPGA pin) is called "clkin_50" via the "[get_ports ]" command. The clock name doesn't have to match the port name, but I find it useful to do so.