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Altera_Forum
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8 years ago

Getting 'Timing requirements not met' as critical warning

Hi, I have created a design and would like to compile the design in order to create a binary file for the CPLD. However when I try to compile the design, it outputs a warning saying that the timing r...
Altera_Forum's avatar
Altera_Forum
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8 years ago

Ah, I see what you are doing. Ideally you shouldn't use clocks generated in logic as actual clocks. Instead the clock divider would generate a 1-fast-clock-cycle pulse every 2048000 clock cycles. You would then use this pulse as an enable signal for your registers which are instead clocked by the fast clock. That way they only get clocked once every 2048000 cycles.

Given you are dealing with low frequencies, it shouldn't be such an issue (though you will get a very jittery clock). If you continue with your approach you will need the create_generated_clock command.