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Altera_Forum
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8 years ago

Getting 'Timing requirements not met' as critical warning

Hi, I have created a design and would like to compile the design in order to create a binary file for the CPLD. However when I try to compile the design, it outputs a warning saying that the timing r...
Altera_Forum's avatar
Altera_Forum
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8 years ago

Thanks. So if I used the top-module clock input to create the inner clk_out, then I only need to create_clock for the top-module clock, right?

If I only use create_clock for the top-module clock and not the internal signal, I get the following warning: 

Warning (332060): Node: clk_divider:clk_module|signal_level was determined to be a clock but was found without an associated clock assignment.
Info (13166): Register fsm:fsm|current_state.READ_STATE is being clocked by clk_divider:clk_module|signal_level