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Honored Contributor
Honored ContributorGetting 'Timing requirements not met' as critical warning
Hi, I have created a design and would like to compile the design in order to create a binary file for the CPLD. However when I try to compile the design, it outputs a warning saying that the timing r...
Altera_ForumHonored Contributor
Honored ContributorYou shouldn't need to define output clocks. Only inputs.
If you do want to define an output clock, that is done using a different command:
# Create a generated clock: -name = name of new clock, -divide_by = output frequency is input divided by this, -source = original clock, then end of line is the target signal where output clock is.
create_generated_clock -name clk_divider_out -divide_by 2048000 -source clk clk_divider:clk_module|signal_level
