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Altera_Forum
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8 years ago

Getting 'Timing requirements not met' as critical warning

Hi, I have created a design and would like to compile the design in order to create a binary file for the CPLD. However when I try to compile the design, it outputs a warning saying that the timing r...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Thanks for the reply.

Yes, it seems like the .sdc was missing. I have added the following lines into my .sdc file: 

create_clock -period 488.281 -name clk clk
create_clock -period 1000000000 -name clk_divider:clk_module|signal_level clk_divider:clk_module|signal_level

For clk I have set to 488.281 (2.048 MHz) and signal_level I have set to 1000000000 (1 Hz) since I want to have clk_divider (clk_out output) as 1 Hz clock. However, I get a warning saying that: 

Warning (332049): Ignored create_clock at synopsys-design-constraints.sdc(2): Time value "1000000000" is not valid Info (332050): create_clock -period 1000000000 -name clk_divider:clk_module|signal_level clk_divider:clk_module|signal_level

What have I done wrong? Thanks