Getting 'TCL READ VARNAME' error message while simulating.

Successfully compiled n-bit shift register Design & Test bench codes (Verilog).

But, as tried for RTL simulation , it throws an error by stating a message as below

Error: Error: NativeLink simulation flow was NOT successful.

There was no issue with the simulator (simulation worked for previous designs).

Help me to solve this issue.

These are the error messages I've got so far,

Error: TCL READ VARNAME
Error: Error: NativeLink simulation flow was NOT successful
Error (23031): Evaluation of Tcl script c:/intel_fpga/16.1/quartus/common/tcl/internal/nativelink/qnativesim.tcl unsuccessful
Error: Quartus Prime Shell was unsuccessful. 3 errors, 1 warning
Error: Peak virtual memory: 4835 megabytes
Error: Processing ended: Mon Jun 14 11:06:54 2021
Error: Elapsed time: 00:00:45
Error: Total CPU time (on all processors): 00:00:01
Error (293001): Quartus Prime Flow was unsuccessful. 5 errors, 2 warnings

I would like to appreciate your time and consideration,

Thanks & Regards

JUNAID.K