Forum Discussion
junaid
New Contributor
New ContributorGetting 'TCL READ VARNAME' error message while simulating.
Successfully compiled n-bit shift register Design & Test bench codes (Verilog).
But, as tried for RTL simulation , it throws an error by stating a message as below
Error: Error: NativeLink simula...
Nurina
Regular Contributor
Regular ContributorHi,
Are you using Standard edition? This error is something that can be ignored: https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/tools/2018/error--23031---evaluation-of-tcl-script--intel-quartus-prime-sys.html
Regards,
Nurina
