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junaid's avatar
junaid
Icon for New Contributor rankNew Contributor
5 years ago

Getting 'TCL READ VARNAME' error message while simulating.

Successfully compiled n-bit shift register Design & Test bench codes (Verilog). But, as tried for RTL simulation , it throws an error by stating a message as below Error: Error: NativeLink simula...
Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

We did not receive any response to the previous question/reply/answer that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.

Regards,
Nurina

PS: If you find any comment from the community or Intel Support to be helpful, feel free to give Kudos.