--- Quote Start ---
Hi,
1.Run: i++ -march="Arria10" counter.cpp command to generate a.prj folder in your directory.
2.And open vsim.wlf from a.prj/verification directory to view the waveform.
Refer the link section 6
https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/hls/ug-hls.pdf --- Quote End ---
Here are my results:
C:\intelFPGA_lite\17.1\hls\examples\counter>i++ -march="Arria10" counter.cpp
a.exe : warning LNK4088: image being generated due to /FORCE option; image may not run
There is no
vsim.wlf in
a.prj/verification directory.
The contents of
verification are these:
\---verification
| compile.cmd
| modelsim.ini
| tb.qsys
| tb.sopcinfo
|
\---tb
| tb.cmp
| tb.csv
| tb.html
| tb.sip
| tb.spd
| tb_generation.rpt
|
+---altera_irq_mapper_171
| \---sim
| tb_altera_irq_mapper_171_dsk4veq.sv
|
+---avalon_concatenate_singlebit_conduits_10
| \---sim
| tb_avalon_concatenate_singlebit_conduits_10_bjzeuhq.sv
|
+---avalon_conduit_fanout_10
| \---sim
| tb_avalon_conduit_fanout_10_wcpjniy.sv
|
+---avalon_split_multibit_conduit_10
| \---sim
| tb_avalon_split_multibit_conduit_10_dlmo3na.sv
|
+---count_10
| \---sim
| tb_count_10_sa5e6hy.v
|
+---count_internal_10
| \---sim
|
|
|
|
+---hls_sim_clock_reset_10
| \---sim
| hls_sim_clock_reset.sv
|
+---hls_sim_component_dpi_controller_10
| \---sim
| hls_sim_component_dpi_controller.sv
| hls_sim_stream_sink_dpi_bfm.sv
| hls_sim_stream_source_dpi_bfm.sv
|
+---hls_sim_main_dpi_controller_10
| \---sim
| hls_sim_main_dpi_controller.sv
|
\---sim
| tb.v
|
+---aldec
| rivierapro_setup.tcl
|
+---cadence
| | cds.lib
| | hdl.var
| | ncsim_setup.sh
| |
| \---cds_libs
| tb_altera_irq_mapper_171.cds.lib
| tb_avalon_concatenate_singlebit_conduits_10.cds.lib
| tb_avalon_conduit_fanout_10.cds.lib
| tb_avalon_split_multibit_conduit_10.cds.lib
| tb_count_10.cds.lib
| tb_count_internal_10.cds.lib
| tb_hls_sim_clock_reset_10.cds.lib
| tb_hls_sim_component_dpi_controller_10.cds.lib
| tb_hls_sim_main_dpi_controller_10.cds.lib
|
+---mentor
| | msim_compile.tcl
| | msim_run.tcl
| | msim_setup.tcl
| |
| \---libraries
| | _info
| |
| +---tb_altera_irq_mapper_171
| | _info
| | _lib.qdb
| | _lib1_0.qdb
| | _lib1_0.qpg
| | _lib1_0.qtl
| | _vmake
| |
| +---tb_avalon_concatenate_singlebit_conduits_10
| | _info
| | _lib.qdb
| | _lib1_0.qdb
| | _lib1_0.qpg
| | _lib1_0.qtl
| | _vmake
| |
| +---tb_avalon_conduit_fanout_10
| | _info
| | _lib.qdb
| | _lib1_0.qdb
| | _lib1_0.qpg
| | _lib1_0.qtl
| | _vmake
| |
| +---tb_avalon_split_multibit_conduit_10
| | _info
| | _lib.qdb
| | _lib1_0.qdb
| | _lib1_0.qpg
| | _lib1_0.qtl
| | _vmake
| |
| +---tb_count_10
| | _info
| | _lib.qdb
| | _lib1_0.qdb
| | _lib1_0.qpg
| | _lib1_0.qtl
| | _vmake
| |
| +---tb_count_internal_10
| | _info
| | _lib.qdb
| | _lib1_0.qdb
| | _lib1_0.qpg
| | _lib1_0.qtl
| | _vmake
| |
| +---tb_hls_sim_clock_reset_10
| | | _info
| | | _lib.qdb
| | | _lib1_0.qdb
| | | _lib1_0.qpg
| | | _lib1_0.qtl
| | | _vmake
| | |
| | \---_dpi
| | dpi.tfdb
| |
| +---tb_hls_sim_component_dpi_controller_10
| | | _info
| | | _lib.qdb
| | | _lib1_0.qdb
| | | _lib1_0.qpg
| | | _lib1_0.qtl
| | | _vmake
| | |
| | \---_dpi
| | dpi.tfdb
| |
| +---tb_hls_sim_main_dpi_controller_10
| | | _info
| | | _lib.qdb
| | | _lib1_0.qdb
| | | _lib1_0.qpg
| | | _lib1_0.qtl
| | | _vmake
| | |
| | \---_dpi
| | dpi.tfdb
| |
| \---work
| _info
| _lib.qdb
| _lib1_0.qdb
| _lib1_0.qpg
| _lib1_0.qtl
| _vmake
|
\---synopsys
\---vcsmx
synopsys_sim.setup
vcsmx_setup.sh
When I try to enable signal logging in the simulator with
i++ -march="arria10" -gvhdl counter.cpp, I get the following error:
C:\intelFPGA_lite\17.1\hls\examples\counter>i++ -march="Arria10" -gvhdl counter.cpp
EmitRawText called on an MCStreamer that doesn't support it, something must not be fully mc'ized
aocl-clang: error: clang frontend command failed with exit code 3 (use -v to see invocation)
HLS Clang (Generating testbench object file) FAILED.
Any ideas on what could be wrong :confused:
Honored Contributor
