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I use the same clock (50MHz) for Signal Tap, that clocks the SPI Logic in my FPGA design.
For me, it seems as if the error always happens while the on chip Signal Tap logic offloads it's data to the computer. Sometimes it captures 2 or 3 events, e.g. the first transfer, then the 25th transfer and so on, but nothing between because Signal Tap is busy offloading it's data in between. So is there any option, that the on chip logic always stores data when the trigger condition happens but waits until I tell it to transfer the data to the computer? This could make it possible to just watch the data at the last moment the trigger condition happened.
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Did you ever solve this?
I am running into the same issue.
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