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Hi,
I'm debugging a communication Interface between my FPGA Design and an external Microcontroller. It should transfer about 1000 packets of data via SPI, but always fails during the transfer. Sometimes it fails after transferring 10 Packets, sometimes it fails after transferring 50 packets. It always seems to miss a change of the chip select input signal, comming from the Microcontroller, so I tried to set the trigger Condition to "falling edge" for the chip select signal. Now when I start signal tap with the Autorun Analysis Button, it triggers the first falling edge of the chip select signal and stops then. But what I expect signal tap to do is recapturing my signals every time chip select has a falling edge, so that it stops at the last time the signal changed and I'm able to see all signal states at that moment. If I run Signal Tap with only don't care trigger conditions, I'm able to see where the packet counter stopped, so I'm sure that chip select went low several times after the first event captured. So what is the problem here and how do I configure Signal tap to behave the way I want it to?
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check your timing and clocking as well as signaltap clock that samples the chip select. Ideally I will use same clock(or faster) in signaltap as the one on the register I monitor.
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