getting crazy with FSM in VHDL. The FSM runs weird and misbehavior

Input ports in VHDL do not need to be defaulted to 'Z'. Only inout ports can use 'Z'. The default will be overridden if it's connected to an internal signal. And logic inside an FPGA can only be '1' or '0' so will get changed at synthesis time.

I was worried about FPGA_CLK because you called it CLK and thought you might be using it as a clock elsewhere in the FPGA. this is bad practice. If it's going off as an interrupt only, then it should be ok (but its bad naming to call it _CLK, better called _IRQ)

Testbenches are code you have written (usually in HDL) to test the functionality of your VHDL code. It is NOT synthesised, it is run through a simulator. You can then check all the outputs from your code to ensure they behave as you expect. There are plenty of tutorials around on the internet about how to write testbenches.