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Honored Contributor
Honored Contributorgetting crazy with FSM in VHDL. The FSM runs weird and misbehavior
background: To Let FPGA (cyclone 3) communication with a DSP board. i am trying to send three datas from DSP board to the FPGA board. code: library ieee;use ieee.std_logic_1164.all;
u...
Altera_ForumHonored Contributor
Honored ContributorDid you debug this in a testbench?
Did you heed the synthesis warning about infered latches in your "second" process? you have signals here that are not set in all processes, which means latches will be infered (which are not a good idea). Other points of concern - why do you have an unused inout port? why do you have in ports that default to 'Z'? Why do you have a logic generated clock output?
