Get value from output vector/ output 8 bit binary on 7 segment display

Hello all,

I am trying to implement an eight bit carry look ahead adder. But my main issue is that I do not know how to output the sum which is an 8-bit out std_logic vector to a seven segment display. As per this youtube video (https://www.youtube.com/watch?v=vkkgyoc4zra), I was able to implement the 8 bit to bcd circuit (component binbcd in my code) and through this link (http://vhdlguru.blogspot.com/2010/03/vhdl-code-for-bcd-to-7-segment-display.html) I am able to output the bcd on the seven segment display (called printOut in my code). However I don't know how to fully integrate every thing in my code. I was thinking that I could declare a signal called output and set the value of sum to output by doing output <= sum. But then I get the error

Error (10309): VHDL Interface Declaration error in cla4_add_subtract.vhd(51): interface object "sum" of mode out cannot be read. Change object mode to buffer.

How do I go about reading from the sum or better yet how do I output 8 bit std_logic_vector to 7 segment display?

library IEEE;
use IEEE.std_logic_1164.all;
entity cla4_add_subtract is
    port(a, b: in std_logic_vector(7 downto 0);
        cin: in std_logic;
        subtract: in std_logic;
        sum: out std_logic_vector(7 downto 0);
        cout: out std_logic;
        overflow: out std_logic);
end cla4_add_subtract;
    
architecture cla4_add_subtract_arch of cla4_add_subtract is
    component mux2to1
        port(
            a, b: in std_logic_vector(7 downto 0);
            sel: in std_logic;
            y: out std_logic_vector(7 downto 0));
    end component;
    
    component claFour
        port( a, b: in std_logic_vector(7 downto 0);
            carryin: in std_logic;
            sum: out std_logic_vector(7 downto 0);
            cgout, cpout, overflow: out std_logic);
    end component;
    
    component binbcd
        port(bin : std_logic_vector(7 downto 0);
            p: out std_logic_vector(9 downto 0));
    end component;
    
    component printOut
        port(digit: in std_logic_vector(3 downto 0);
                print: out std_logic_vector(6 downto 0));
    end component;
    
    signal carry: std_logic;
    signal b_not: std_logic_vector(7 downto 0);
    signal b_actual: std_logic_vector(7 downto 0);
    begin
        b_not <= not b;
        carry <= cin;
        MUX_SUB:
        mux2to1
    port map (b, b_not, subtract, b_actual);
    ADD0:
        claFour
    port map (a, b_actual, carry, sum, cout, open, overflow);
library IEEE;
use IEEE.std_logic_1164.all;
entity printOut is
        port(digit:in std_logic_vector(3 downto 0);
                print:out std_logic_vector(6 downto 0));
    end printOut;
architecture parch of printOut is
begin
    process(digit)
        begin 
        case  digit is
            when "0000"=> print <="0000001";  -- '0'
            when "0001"=> print <="1001111";  -- '1'
            when "0010"=> print <="0010010";  -- '2'
            when "0011"=> print <="0000110";  -- '3'
            when "0100"=> print <="1001100";  -- '4'
            when "0101"=> print <="0100100";  -- '5'
            when "0110"=> print <="0100000";  -- '6'
            when "0111"=> print <="0001111";  -- '7'
            when "1000"=> print <="0000000";  -- '8'
            when "1001"=> print <="0000100";  -- '9'
            when others=> print <="1111111";
        end case;
    end process;
end parch;