Generic Priority Encoder

What is priority encoder? I have never heard of it as a concept but I know some of us use this word for if/else/... and I am not sure if case statement is priority as it implies parallel logic. So it will help to know what is your priority encoder inputs/outputs and what is'it meant to do?

TO_BE_DONE

using if/elsif:

Read about priority encoders here: http://www.electronics-tutorials.ws/combination/comb_4.html

Thanks for the link. After a quick glance it looks like(unless proved otherwise) this not really fpga area but rather combinatorial circuits meant for some ICs. FPGAs do not have this problem to merit this type of design. But it is interesting to know that.

mbmckeon,

As rbugalho pointed out, the case and if-elsif-else example don't implement the same logic, and there is apparently a typo in the first lines of the if-elsif code. So I#m not totally sure about the intended function.

t2:
IF typ = 2 generate
process(s_CLOCK, s_RESET)
begin
if (s_RESET = '1') then
s_DEC_IN_Q1 <= (others=>'0');
s_DEC_OUT_Q1 <= (others=>'0');
elsif (s_CLOCK'event and s_CLOCK='1') then
   s_DEC_IN_Q1 <= s_DEC_IN;
   for I in 0 to NBIT-1 loop
      if s_DEC_IN_Q1(i) = '1' then
         s_DEC_OUT_Q1 <= std_logic_vector(to_unsigned(i,nbita)+1);
         exit;
      end if;
      s_DEC_OUT_Q1 <= (others => '0');
   end loop;
end if;
end process; 
end generate;
t3:
IF typ = 3 generate
pe: altpriority_encoder
generic map (
   lsb_priority => "YES",
   pipeline => 1,
   width => nbit,
   widthad => nbita)
port map (
   aclr => S_RESET,
   clock => S_CLOCK,
   data=> s_DEC_IN,
   q => s_DEC_OUT
); 
process(s_CLOCK, s_RESET)
begin
   if (s_RESET = '1') then
      s_DEC_OUT_Q1 <= (others=>'0');
   elsif (s_CLOCK'event and s_CLOCK='1') then
      s_DEC_OUT_Q1 <= std_logic_vector(unsigned(s_DEC_OUT)+1);
   end if;
end process; 
end generate;

The behavior I want is in example 1. I didn't verify example 2, and looking back there is probably a mistake anyway (zeros to right should be don't care, after ones). In either case, what I meant about being optimal is speed wise, I don't care if it uses more or less resources. My design ideally would be able to run in excess of 333 MHz which might not be realistic, but the closer I can get to that number or beyond the better, and I want to minimize logic layers. FvM I did find the code for example t2 in another book, and is nice and compact code, but I don't know what performance I can achieve yet. The input width's could be anywhere between 12-64. I was not able to find any information on altpriority_encoder, I can't find it in the MegaWizard. Where exactly is it located?

I also searched for the altpriority_encoder to no avail!