As rbugalho pointed out, the case and if-elsif-else example don't implement the same logic, and there is apparently a typo in the first lines of the if-elsif code. So I#m not totally sure about the intended function.
I assume that lsb_priority with 1-based index is intended. See below two parameterizable variants. altpriority_encoder is faster and needing fewer logic elements than the behavioral description. I used two pipeline levels according to the original example.
If you want to enforce a faster implementation in arithmetic mode (using carry chain), there are other options. The code won't be that straightforward, however.
To decide about the implementation, we need to know the intended fmax and maximum number of bits.
t2:
IF typ = 2 generate
process(s_CLOCK, s_RESET)
begin
if (s_RESET = '1') then
s_DEC_IN_Q1 <= (others=>'0');
s_DEC_OUT_Q1 <= (others=>'0');
elsif (s_CLOCK'event and s_CLOCK='1') then
s_DEC_IN_Q1 <= s_DEC_IN;
for I in 0 to NBIT-1 loop
if s_DEC_IN_Q1(i) = '1' then
s_DEC_OUT_Q1 <= std_logic_vector(to_unsigned(i,nbita)+1);
exit;
end if;
s_DEC_OUT_Q1 <= (others => '0');
end loop;
end if;
end process;
end generate;
t3:
IF typ = 3 generate
pe: altpriority_encoder
generic map (
lsb_priority => "YES",
pipeline => 1,
width => nbit,
widthad => nbita)
port map (
aclr => S_RESET,
clock => S_CLOCK,
data=> s_DEC_IN,
q => s_DEC_OUT
);
process(s_CLOCK, s_RESET)
begin
if (s_RESET = '1') then
s_DEC_OUT_Q1 <= (others=>'0');
elsif (s_CLOCK'event and s_CLOCK='1') then
s_DEC_OUT_Q1 <= std_logic_vector(unsigned(s_DEC_OUT)+1);
end if;
end process;
end generate;