Generation of STP file for SignalTap

Hello,

If you start using signaltap logic analyser it generates .stp as a result of your configuraton in signaltap. (make a configuration and save it)

You will have trouble finding some signals in the node list, to solve this you can define the attribute "keep" in your code, then some invisible nodes will become visible with their orignial name.

Example:

-- declare --
attribute keep: boolean;
signal    reset_p    : std_logic:='0';
signal    done       : std_logic:='0';
signal    enable     : std_logic:='0';
 
attribute keep of reset_p : signal is true;
attribute keep of done    : signal is true;
attribute keep of enable  : signal is true;

For your problem you might consider using modelsim and write a simulation bench.

This enables you to simulate your design. This approach can be much more productive than signaltap.

On the other hand: are you 100% sure that ram is the issue with Quartus?

Of course it depends on the size of your design, but Quartus runs well in 8GB ram for small designs.

Best Regards,

Johi.