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Altera_Forum's avatar
Altera_Forum
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10 years ago

Generating higher frequency sine waves from 5MHz RAM

Currently using the Stratix III EP3SL150F1152 DSP Developers Kit in Verilog. I generated one period sine wave 5MHz sampling at 250MHz (50 samples in a .MIF file from MATLAB ). I ported it to a RAM block (altsyncram, 5MHz with a clk in at 250MHZ) and used a counter module (inc to pull the samples to generate a continuous waveform out to a 16-bit DAC (oscoped and SignalTapped). My FPGA is receiving a 250MHz clock, the DAC is getting 500MHz from DDRIO (Double Data Rate), and the RAM/counter modules are receiving 250MHz. How approach can I take to output different frequencies of 105-135MHz sine waves and not violate timing and erroneous outputs? I can double my PLL to 500MHz in design and MATLAB (100 samples for 5MHz sampled at 500MHz) to start at 10MHz, but I feel skipping addresses in my counter module will lead to undersampling when going above 20-25MHz, outputting incorrect data. I realize dual edge clocking to sample at posedge and negedge does not apply in synthesizing flops unless I use two always blocks; which is why I utilized PLL to use single edged logic. Any guidance is greatly appreciated.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    You better use a standard NCO approach based on altera nco core.

    I am not sure I understand your figures of 250, 500?
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    --- Quote Start ---

    You better use a standard NCO approach based on altera nco core.

    I am not sure I understand your figures of 250, 500?

    --- Quote End ---

    I'm not too familiar with the NCO approach, but I would like to keep my Vpp to be 1. In MATLAB I had my amplitude to be 0.5. Correct me if I'm wrong, but the clocking into my modules are what my sampling frequency is. It would have to match the MATLAB implemented into a MIF file and in my Verilog design. So by changing my input clock from 250MHz to 500MHz through PLL, my sampling frequency will give me double the samples (100 samples for 5MHz at 250MHz sampling frequency), raising the threshold of address manipulation before undersampling.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    --- Quote Start ---

    I'm not too familiar with the NCO approach, but I would like to keep my Vpp to be 1. In MATLAB I had my amplitude to be 0.5. Correct me if I'm wrong, but the clocking into my modules are what my sampling frequency is. It would have to match the MATLAB implemented into a MIF file and in my Verilog design. So by changing my input clock from 250MHz to 500MHz through PLL, my sampling frequency will give me double the samples (100 samples for 5MHz at 250MHz sampling frequency), raising the threshold of address manipulation before undersampling.

    --- Quote End ---

    You are following the equation: Fo = Fs/samples per cycle

    That is correct and you want to change Fo by changing Fs. You can but in most cases we change samples per cycle and keep Fs.

    just instantiate an nco core. You don't need to worry about how it works internally but you will input into it increment value for your target Fo.