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You better use a standard NCO approach based on altera nco core.
I am not sure I understand your figures of 250, 500?
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I'm not too familiar with the NCO approach, but I would like to keep my Vpp to be 1. In MATLAB I had my amplitude to be 0.5. Correct me if I'm wrong, but the clocking into my modules are what my sampling frequency is. It would have to match the MATLAB implemented into a MIF file and in my Verilog design. So by changing my input clock from 250MHz to 500MHz through PLL, my sampling frequency will give me double the samples (100 samples for 5MHz at 250MHz sampling frequency), raising the threshold of address manipulation before undersampling.
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