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kh12's avatar
kh12
Icon for New Contributor rankNew Contributor
3 years ago

Generating a Simulation File for ATLPLL IP

Hello, I am using the MAX10 dev board. Following instructions for creating the PLL is easy, however as seen in the following document (https://www.ece.ucdavis.edu/~bbaas/180/tutorials/using.a.PLL.pdf...
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi,

Go to Assignments > Settings > EDA Tool Settings > Simulation. Then set Tool name and EDA Netlist Writer settings. Should see simulation file generated after EDA Netlist Writer compilation. Remember to set the Tool Executable location in Tools > Options > EDA Tool Options

Best Regards,

Sheng

p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.

kh12's avatar
kh12
Icon for New Contributor rankNew Contributor
3 years ago

Hello,

I am looking to generate a verilog file to run on modelsim. With past versions (using altera pll instead of ALTPLL) I used to get a folder like: pllname_0002 and in it I had a .qip file and a .v file. When I follow these instructions I don't get that simulation verilog file.